1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device having a higher tolerance to metal pollution and a method of manufacturing the semiconductor device.
2. Description of the Background Art
A semiconductor device having an SOI structure (hereinafter referred to as an SOI device) to be formed on an SOI substrate in which a buried oxide film and an SOI (Silicon On Insulator) layer are provided on a silicon substrate is characterized in that a parasitic capacitance can be reduced, an operation can be carried out at a high speed and power consumption can be reduced, and is used for portable equipment and the like.
In order to implement a high speed operating circuit, a technique for reducing a resistance is essential. As the technique for reducing a resistance, generally, a method of forming a metal compound layer (silicide layer) in self-alignment in a gate wiring or a source-drain region of a transistor constituting the circuit.
For example, as shown in FIG. 83 of Japanese Patent Application Laid-Open No. 6-204334 (1994), a metal layer such as Ti (titanium) or Co (cobalt) is deposited through sputtering or the like over an upper portion of a gate electrode formed of polysilicon and a source-drain region and a heat treatment is carried out for a short time so that a silicide layer is formed. In general, it has been known that the metal layer does not form the silicide layer over an isolating film, an oxide film such as a side wall oxide film of a gate electrode, and a nitride film at this time.
Depending on the conditions of the heat treatment or the kind of an insulating film, however, a metallic element such as Co is diffused into the insulating film and reaches a silicon layer provided under the insulating film so that a silicide is formed therein in some cases.
For example, there is a problem in that a circuit malfunctions due to an increase in a junction leakage current when the silicide is formed in a PN junction region.
In recent years, moreover, a wiring material tends to be changed from a conventional Al (aluminum)xe2x80x94Cu (copper) alloy wiring to a Cu wiring or the like due to a reduction in a resistance of a wiring. Correspondingly, it has been reported that a characteristic of a device is deteriorated due to the diffusion of Cu.
In addition, the number of process steps is increased with microfabrication of a semiconductor device and multilayered wiring. Consequently, the metal pollution often occurs. When a metal pollutant is segregated into a junction interface, the junction leakage current is increased and the circuit malfunctions as described above.
A conventional silicide process will be described with reference to FIGS. 62 to 65.
First of all, an SOI substrate 10 in which a buried oxide film 2 and an SOI layer 3 are provided on a silicon substrate 1 is prepared as shown in FIG. 62 and a trench isolation oxide film STI is selectively formed as an isolating film in a surface of the SOI layer 3, thereby defining a region QR forming a MOS transistor and a region RR forming a resistive element.
A trench isolation oxide film STI is also referred to as a shallow trench isolation oxide film (STI) and has a well region WR provided thereunder so that elements are not electrically isolated completely from each other. In some cases, therefore, the trench isolation oxide film STI is also referred to as a partial isolation oxide film (PTI).
After the trench isolation oxide film STI is formed, a gate oxide film GO and a gate electrode GT are selectively formed on the SOI layer 3 of the MOS transistor region QR.
Then, a resist mask RI is formed such that the region QR is to be an opening, and an impurity ion of the same conductivity type as that of the source-drain region in the SOI layer is implanted by using the gate electrode GT as a mask. Thus, an extension region EX is formed in self-alignment.
The extension region EX is a shallower diffusion region than a source-drain region which is to be formed at a subsequent step, and is formed by implanting the impurity ion in a lower concentration than that of the source-drain region or in substantially the same concentration as that of the source-drain region such that it acts as a part of the source-drain region.
At a step shown in FIG. 63, next, a side wall spacer SW is formed on a side surface of the gate electrode GT, a resist mask R2 is formed such that the regions QR and RR are to be openings, and an impurity ion is implanted into the SOI layer 3 to form a source-drain region SD in self-alignment. At this time, the impurity is also implanted into the resistive element region RR so that a resistive layer RL is formed.
At a step shown in FIG. 64, subsequently, an insulating film IF is selectively formed on the SOI layer 3 in the region RR to prevent the formation of a silicide layer. Then, a metal layer such as Ti or Co is deposited through sputtering or the like and a silicide reaction is promoted by a heat treatment.
The silicide reaction is achieved by causing an exposed silicon layer to react to the metal layer provided thereon through a heat treatment at a low temperature for a short time. Since the metal layer formed on an insulating film such as an oxide film is not silicided, it is removed in a subsequent removing process. Then, a silicide film having a stable structure is formed through a second heat treatment.
FIG. 64 shows a state obtained after an unreacted metal film is removed, and a silicide layer SS is formed over the source-drain region SD, the gate electrode GT and the resistive layer RL. A silicide layer SS is formed in two positions interposing an insulating film IF over the resistive layer RL and acts as two electrodes of the resistive element.
At a step shown in FIG. 65, then, an interlayer insulating film IZ is formed on the SOI layer 3, and a plurality of contact portions CH reaching the silicide layer SS formed on the source-drain layer SD and the resistive layer RL are provided through the interlayer insulating film IZ. Thus, an SOI device 90 is constituted.
Referring to FIGS. 62 to 65, the SOI device 90 formed on the SOI substrate 10 has been described. FIG. 66 shows a bulk device 90A formed on a bulk silicon substrate 1.
In the bulk device 90A, a deeper trench isolation oxide film ST2 is provided in place of the trench isolation oxide film ST1. Since other structures are the same as those of the SOI device 90 shown in FIG. 65, the same structures have the same reference numerals and repetitive description will be omitted.
As described above, the silicide reaction causes the exposed silicon layer to react to the metal layer provided thereon through the heat treatment (first heat treatment) at a low temperature for a short time and the unreacted metal film is removed, and the silicide film having a stable structure is then formed through the second heat treatment. There is a possibility that a metal constituting the metal film might be diffused into the insulating film through the first heat treatment or the unreacted metal film might be removed insufficiently to cause the metal to remain in a very small amount over the insulating film and to be diffused into the insulating film through the second heat treatment or a heat treatment in a subsequent process. In such a case, the metal layer reaching a surface of the silicon layer forms a silicide. For example, in the case in which the silicide is formed in a PN junction region, a junction leakage current is caused. In the case in which the silicide is formed in the vicinity of an interface between a gate insulating film and a silicon layer, reliability of the gate insulating film is deteriorated.
As shown in FIG. 66, it is apparent that the same problem arises in the device 90A formed on the bulk silicon layer 1.
A first aspect of the present invention is directed to a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, an isolation film formed in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, a PN junction portion formed by two semiconductor regions of different conductivity types in the semiconductor layer provided under the isolation film, and a polysilicon film provided in a position opposed to a top of the PN junction portion with the isolation film interposed therebetween across the two semiconductor regions.
A second aspect of the present invention is directed to the semiconductor device, wherein the polysilicon film is formed in an upper portion of an outside of the isolation film, and a formation width of the polysilicon film is set such that a length Lg from a position in the polysilicon film corresponding to a position of the PN junction portion to an end of the polysilicon film and a thickness Tst of the isolation film satisfy an equation of 0.5 Lg less than Tst less than 20 Lg.
A third aspect of the present invention is directed to the semiconductor device, wherein the semiconductor elements include a MOS transistor, and a thickness of the polysilicon film is equal to that of a gate polysilicon film constituting a gate electrode of the MOS transistor.
A fourth aspect of the present invention is directed to the semiconductor device, wherein the semiconductor elements include a MOS transistor, and a thickness of the polysilicon film is smaller than that of a gate polysilicon film constituting a gate electrode of the MOS transistor.
A fifth aspect of the present invention is directed to the semiconductor device, wherein the PN junction portion is extended along a provision pattern of the isolation film, and the polysilicon film is provided along the PN junction portion.
A sixth aspect of the present invention is directed to the semiconductor device, wherein the polysilicon film is formed in the isolation film, and has a substantially uniform thickness across the two semiconductor regions.
A seventh aspect of the present invention is directed to the semiconductor device, wherein the isolation film has an upper oxide film and a lower oxide film which are provided in upper and lower portions of the polysilicon film, and an oxide film spacer for covering side surfaces of the upper oxide film, the polysilicon film and the lower oxide film.
An eighth aspect of the present invention is directed to the semiconductor device, wherein the isolation film has an upper oxide film and a lower oxide film which are provided in upper and lower portions of the polysilicon film, and an oxide film provided on a side surface of the polysilicon film.
A ninth aspect of the present invention is directed to a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, an isolation film provided in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, a PN junction portion formed by two semiconductor regions of different conductivity types in the semiconductor layer provided under the isolation film, and the isolation film including a nitride film provided in a position corresponding to a top of the PN junction portion and having a substantially uniform thickness across the two semiconductor regions, and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film.
A tenth aspect of the present invention is directed to a semiconductor device comprising an SOI substrate including a semiconductor substrate, a buried oxide film provided on the semiconductor substrate and an SOI layer provided on the buried oxide film, a plurality of semiconductor elements formed on the SOI layer, and an isolation film provided in a surface of the SOI layer, the semiconductor elements being electrically isolated from each other by the isolation film, the isolation film including a complete trench reaching the buried oxide film penetrating through the SOI layer and a partial trench leaving a well region thereunder without penetrating through the SOI layer which are continuously provided, an internal wall insulating film provided on internal walls of the complete trench and the partial trench, an internal polysilicon film provided to fill in the complete trench and to be extended over a bottom face of the partial trench, and an upper insulating film provided to cover the internal polysilicon film and surrounding the internal polysilicon film together with the internal insulating film, thereby electrically insulating the internal polysilicon film.
An eleventh aspect of the present invention is directed to the semiconductor device, wherein the internal polysilicon film is restrictively provided in the partial trench so as not to get over the internal wall insulating film formed on a side wall of the partial trench.
A twelfth aspect of the present invention is directed to a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, an isolation film provided in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, a PN junction portion formed by two semiconductor regions of different conductivity types in the semiconductor layer provided under the isolation film, and a local crystal defect region provided along the PN junction under the isolation film on at least one of sides in the two semiconductor regions.
A thirteenth aspect of the present invention is directed to the semiconductor device, wherein the crystal defect region is a region in which an impurity of the same conductivity type as a conductivity type of the semiconductor region having the crystal defect region formed therein is introduced in a relatively high concentration.
A fourteenth aspect of the present invention is directed to the semiconductor device, wherein the crystal defect region is a region in which an impurity of a different conductivity type from the conductivity type of the semiconductor region having the crystal defect region formed therein is introduced in a relatively high concentration.
A fifteenth aspect of the present invention is directed to a semiconductor device comprising an SOI substrate including a semiconductor substrate, a buried oxide film provided on the semiconductor substrate and an SOI layer provided on the buried oxide film, a plurality of semiconductor elements formed on the SOI layer, an isolation film provided in a surface of the SOI layer, the semiconductor elements being electrically isolated from each other by the isolation film, a PN junction portion formed by two semiconductor regions of different conductivity types in the SOI layer provided under the isolation film, and a first polysilicon film buried to penetrate through the vicinity of the PN junction portion on at least one of sides in the two semiconductor regions.
A sixteenth aspect of the present invention is directed to the semiconductor device, wherein the semiconductor elements include a MOS transistor, the MOS transistor having a source-drain region provided in a surface of the SOI layer, and a second polysilicon film is further buried to penetrate through the source-drain region adjacent to the isolation film.
A seventeenth aspect of the present invention is directed to the semiconductor device, further comprising first and second local crystal defect regions provided in the vicinity of an interface between the silicon substrate and the buried oxide film under the first and second polysilicon films.
An eighteenth aspect of the present invention is directed to a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, an isolation film formed in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, a PN junction portion formed by two semiconductor regions of different conductivity types in the semiconductor layer provided under the isolation film, and an upper nitride film provided in a position opposed to a top of the PN junction portion with the isolation film interposed therebetween across the two semiconductor regions.
A nineteenth aspect of the present invention is directed to the semiconductor device, wherein the semiconductor elements include a MOS transistor, the MOS transistor having a side wall spacer formed of a nitride film which is provided on side surfaces of a gate electrode and a gate insulating film, and a thickness of the upper nitride film is substantially equal to that of the side wall spacer.
A twentieth aspect of the present invention is directed to the semiconductor device, wherein the upper nitride film and the side wall spacer have a two-layered structure, and respective first layers and respective second layers have thicknesses substantially equal to each other.
A twenty-first aspect of the present invention is directed to a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, an isolation film formed in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, and a PN junction portion formed by two semiconductor regions of different conductivity types in the semiconductor layer provided under the isolation film, the isolation film having a plurality of silicon islands therein, the silicon islands being provided in a position corresponding to a top of the PN junction portion in the isolation film across the two semiconductor regions.
A twenty-second aspect of the present invention is directed to the semiconductor device, wherein the semiconductor device is an SOI semiconductor device formed on an SOI substrate including a silicon substrate, a buried oxide film provided on the silicon substrate and an SOI layer provided on the buried oxide film, the semiconductor layer being the SOI layer.
A twenty-third aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising a silicon semiconductor layer, a plurality of semiconductor elements formed on the silicon semiconductor layer, and an isolation film formed in a surface of the silicon semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, the method comprising the steps of (a) forming the semiconductor elements and then forming a metal layer to provide a silicide layer over a whole surface, (b) carrying out a heat treatment to cause the metal layer to react to the silicon semiconductor layer, thereby forming a silicide layer, and (c) removing an unreacted metal layer and a surface of the isolation film by a predetermined thickness after the heat treatment.
A twenty-fourth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (c) includes the steps of (c-1) removing the unreacted metal layer by wet etching after the heat treatment, and (c-2) carrying out dry etching for removing the surface of the isolation film by the predetermined thickness after the step (c-1), the isolation film being formed of an oxide film, the step (c-2) including the step of using at least hydrofluoric acid as an etching agent, the predetermined thickness being 2 to 50 nm.
A twenty-fifth aspect of the present invention is directed to the method of manufacturing a semiconductor device, further comprising, prior to the step (c-2), the step of forming a mask setting at least a top of the isolation film to be an opening, the step (c-2) being carried out by using the mask.
A twenty-sixth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, the method comprising the steps of (a) providing a first oxide film, a polysilicon film and a second oxide film on the semiconductor layer, (b) selectively removing the first oxide film, the polysilicon film and the second oxide film, thereby forming a laminated film of a lower oxide film, the polysilicon film and an upper oxide film in a position where the isolation film is to be formed, (c) covering at least a side surface of the polysilicon film with an oxide film, thereby forming the isolation film, and (d) epitaxially growing the semiconductor layer, thereby burying the isolation film in the surface of the semiconductor layer thus grown after the step (c).
A twenty-seventh aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (c) further includes the step of forming an oxide film spacer to cover a side surface of the laminated film.
A twenty-eighth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (c) includes the step of thermally oxidizing the side surface of the polysilicon film, thereby forming an oxide film.
A twenty-ninth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, the method comprising the steps of (a) providing a first oxide film, a nitride film and a second oxide film on the semiconductor layer, (b) selectively removing the first oxide film, the nitride film and the second oxide film, thereby forming a laminated film of a lower oxide film, the nitride film and an upper oxide film in a position where the isolation film is to be formed, and (c) epitaxially growing the semiconductor layer, thereby burying the isolation film in the surface of the semiconductor layer thus grown after the step (b).
A thirtieth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising an SOI substrate including a silicon substrate, a buried oxide film provided on the silicon substrate and an SOI layer provided on the buried oxide film, a plurality of semiconductor elements formed on the SOI layer, and an isolation film provided in a surface of the SOI layer, the semiconductor elements being electrically isolated from each other by the isolation film, the method comprising the steps of (a) selectively removing the SOI layer so as not to reach the buried oxide film and forming a partial trench to leave the SOI layer thereunder, (b) selectively removing the SOI layer in the partial trench and forming a complete trench reaching the buried oxide film penetrating through the SOI layer, (c) forming an internal wall insulating film covering internal walls of the complete trench and the partial trench, (d) forming a polysilicon film to fill in the complete trench and the partial trench, (e) selectively removing the polysilicon film, thereby forming an internal polysilicon film restrictively remaining in the partial trench, and (f) covering the internal polysilicon film and surrounding the internal polysilicon film together with the internal wall insulating film, thereby forming an upper insulating film for electrically insulating the internal polysilicon film.
A thirty-first aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, (a) forming the isolation film and then implanting an impurity ion such that a PN junction portion is formed in the semiconductor layer provided under the isolation film, thereby forming two semiconductor regions of different conductivity types, and (b) implanting an ion from above the isolation film, thereby forming a local crystal defect region in the vicinity of the PN junction portion on at least one of sides of the two semiconductor regions.
A thirty-second aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (b) includes the step of implanting an impurity ion of the same conductivity type as the conductivity type of the semiconductor region having the crystal defect region formed therein.
A thirty-third aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (b) includes the step of implanting an impurity ion of a different conductivity type from the conductivity type of the semiconductor region having the crystal defect region formed therein.
A thirty-fourth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, the semiconductor elements including a MOS transistor, the method comprising the steps of (a) forming the isolation film and then selectively forming a gate electrode and a gate insulating film in the MOS transistor on the semiconductor layer, and (b) covering a whole surface including the gate electrode and the gate insulating film with a nitride film and then selectively removing them, thereby leaving the nitride film as a side wall spacer on side surfaces of the gate electrode and the gate insulating film and leaving the nitride film also in a position opposed to a top of the semiconductor layer with the isolation film interposed therebetween to form an upper nitride film.
A thirty-fifth aspect of the present invention is directed to the method of manufacturing a semiconductor device, wherein the step (b) includes the steps of covering the whole surface with a first nitride film and then selectively removing the first nitride film, thereby forming a first side wall spacer on the side surfaces of the gate electrode and the gate insulating film and leaving the first nitride film also on the isolation film to form a first upper nitride film, and covering a whole surface having the first side wall spacer and the first upper nitride film with a second nitride film and then selectively removing the second nitride film, thereby forming a second side wall spacer covering the first side wall spacer and leaving the second nitride film also on the first upper nitride film to form a second upper nitride film.
A thirty-sixth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, the semiconductor elements being electrically isolated from each other by the isolation film, the method comprising the step of implanting a silicon ion or an oxygen ion in the isolation film and then carrying out annealing at a temperature of 1000 to 1400xc2x0 C., thereby forming a plurality of silicon islands in the isolation film.
A thirty-seventh aspect of the present invention is directed to the semiconductor device, wherein the polysilicon film is connected to have a predetermined electric potential.
According to the first aspect of the present invention, the polysilicon film is provided in the position corresponding to the top of the PN junction portion on the isolation film across the two semiconductor regions. Therefore, a region where an unreacted metal layer remains as a residual metal in the formation of a silicide layer is restricted over the isolation film so that there can be a lower possibility that the residual metal might be diffused into the isolation film by a heat treatment in a process to reach an undesirable portion, for example, the PN junction portion. As a result, a silicide can be prevented from being formed in the PN junction portion and a junction leakage current can be prevented from being generated.
According to the second aspect of the present invention, the formation width of the polysilicon film is set to satisfy the equation of 0.5 Lg less than Tst less than 20 Lg. Consequently, it is possible to obtain a polysilicon film capable of effectively preventing the residual metal from reaching an undesirable portion.
According to the third aspect of the present invention, the thickness of the polysilicon film is set to be equal to that of the gate polysilicon film. Consequently, the polysilicon film can be formed at the step of forming the gate electrode so that the manufacturing process can be simplified.
According to the fourth aspect of the present invention, the thickness of the polysilicon film is set to be smaller than that of the gate polysilicon film. Consequently, an internal residual stress is more relieved than that in the case in which the thickness of the polysilicon film is equal to or greater than that of the gate polysilicon film. Thus, a characteristic can be stabilized.
According to the fifth aspect of the present invention, the polysilicon film is provided along the PN junction portion. Consequently, a silicide can be effectively prevented from being formed in all the regions of the PN junction portion and a junction leakage current can be prevented from being generated.
According to the sixth aspect of the present invention, the polysilicon film having a substantially uniform thickness is provided in the position corresponding to the top of the PN junction portion in the isolation film across the two semiconductor regions. Therefore, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, it reaches the polysilicon film and then reacts to the polysilicon film to form a silicide. Therefore, it is possible to prevent the residual metal from reaching the PN junction portion of the two well regions, for example. Moreover, the residual metal can be prevented from reaching another PN junction portion in the semiconductor layer, for example, a PN junction portion of a well region and a source drain region, a silicide can be prevented from being formed in the PN junction portion and the junction leakage current can be prevented from being generated.
According to the seventh aspect of the present invention, it is possible to obtain a more realistic structure of the isolation film having the polysilicon film therein.
According to the eighth aspect of the present invention, it is possible to obtain a more realistic and simplified structure of the isolation film having the polysilicon film therein.
According to the ninth aspect of the present invention, the nitride film having a substantially uniform thickness is provided in the position corresponding to the top of the PN junction portion in the isolation film across the two semiconductor regions. Therefore, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, it can be prevented from being further diffused after reaching the nitride film. Therefore, it is possible to prevent the residual metal from reaching the PN junction portion of the two well regions, for example. Moreover, the residual metal can be prevented from reaching another PN junction portion in the semiconductor layer, for example, a PN junction portion of a well region and a source-drain region, a silicide can be prevented from being formed in the PN junction portion and the junction leakage current can be prevented from being generated.
According to the tenth aspect of the present invention, the isolation film has such a structure that the complete trench and the partial trench are provided continuously, and the polysilicon film is provided to fill in the complete trench and to be extended over the bottom face of the partial trench. Therefore, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, it reaches the polysilicon film and then reacts to the polysilicon film to form a silicide. Therefore, it is possible to prevent the residual metal from reaching the PN junction portion of the two well regions in the semiconductor layer, for example. Moreover, the residual metal can be prevented from reaching another PN junction portion in the semiconductor layer, for example, a PN junction portion of a well region and a source-drain region, a silicide can be prevented from being formed in the PN junction portion and the junction leakage current can be prevented from being generated.
According to the eleventh aspect of the present invention, the polysilicon film is restrictively provided in the partial trench and is not protruded toward the outside of the isolation film. Therefore, it is possible to prevent drawbacks from being caused by a defective insulation.
According to the twelfth aspect of the present invention, the local crystal defect region is provided along the PN junction in the vicinity of the PN junction portion on at least one of sides in the two semiconductor regions. Therefore, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, the residual metal converges in the crystal defect region constituting the gettering region and can be prevented from reaching the PN junction portion of the two well regions in the semiconductor layer, for example. Moreover, the residual metal can be prevented from reaching another PN junction portion in the semiconductor layer, for example, a PN junction portion of a well region and a source-drain region, a silicide can be prevented from being formed in the PN junction portion and the junction leakage current can be prevented from being generated.
According to the thirteenth aspect of the present invention, the crystal defect region is formed by introducing the impurity of the same conductivity type as the conductivity type of the semiconductor region in a relatively high concentration. Therefore, it is possible to reduce the influence on the well region through the impurity introduction.
According to the fourteenth aspect of the present invention, the crystal defect region is formed by introducing the impurity of a different conductivity type from the conductivity type of the semiconductor region in a relatively high concentration. Therefore, it is possible to increase the degree of freedom in selection of the method of forming the crystal defect region.
According to the fifteenth aspect of the present invention, there is provided the first polysilicon film buried to penetrate through the vicinity of the PN junction portion on at least one of sides in the two semiconductor regions and through the buried oxide film. Therefore, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, it reaches the first polysilicon film and then reacts to the first polysilicon film to form a silicide. Therefore, it is possible to prevent the residual metal from reaching the PN junction portion of the two well regions, for example.
According to the sixteenth aspect of the present invention, there is further provided the second polysilicon film buried to penetrate through the source-drain region adjacent to the isolation film and through the buried oxide film. Therefore, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, it reaches the second polysilicon film and then reacts to the second polysilicon film. Consequently, the residual metal can be prevented from reaching a PN junction portion of a well region and a source-drain region, a silicide can be prevented from being formed in the PN junction portion and the junction leakage current can be prevented from being generated.
According to the seventeenth aspect of the present invention, the first and second local crystal defect regions are provided in the vicinity of the interface between the silicon substrate and the buried oxide film under the first and second polysilicon films. In addition to an original gettering effect of the silicon substrate, therefore, the first and second crystal defect regions act as gettering sites. Consequently, the gettering effect can be enhanced.
According to the eighteenth aspect of the present invention, the upper nitride film is provided in the position corresponding to the top of the PN junction portion on the isolation film across the two semiconductor regions. Therefore, a region where an unreacted metal layer remains as a residual metal in the formation of a silicide layer is restricted over the isolation film so that there can be a lower possibility that the residual metal might be diffused into the isolation film by a heat treatment in a process to reach an undesirable portion, for example, the PN junction portion. Moreover, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, most of metal atoms are deposited in the upper nitride film or on an interface between the upper nitride film and the isolation film and are not diffused into the isolation film. As a result, a silicide can be prevented from being formed in the PN junction portion and the junction leakage current can be prevented from being generated.
According to the nineteenth aspect of the present invention, the thickness of the upper nitride film is substantially equal to that of the side wall spacer of the MOS transistor. Consequently, the upper nitride film can be formed at the step of forming the side wall spacer so that the manufacturing process can be simplified.
According to the twentieth aspect of the present invention, the upper nitride film and the side wall spacer are caused to have a two-layered structure and the respective first layers and the respective second layers are caused to have thicknesses substantially equal to each other. Consequently, the upper nitride film to be the first layer can be formed at the step of forming the first layer of the side wall spacer, the source-drain region is then formed, and the upper nitride film to be the second layer is thereafter formed at the step of forming the second layer of the side wall spacer. Thus, the total formation width of the side wall spacer can be increased and drawbacks can be prevented from being caused by the abnormal growth of the silicide film. In addition, the extension region to be generally formed under the first layer of the side wall spacer can be shortened, a parasitic resistance can be reduced and the characteristic of the MOS transistor is not deteriorated.
According to the twenty-first aspect of the present invention, a plurality of silicon islands are provided in the position corresponding to the top of the PN junction portion in the isolation film across the two semiconductor regions. Therefore, even if an unreacted metal layer remains as a residual metal on the isolation film in the formation of the silicide layer and is diffused into the isolation film by the heat treatment in the process, the residual metal converges in the silicon islands and can be prevented from reaching the PN junction portion of the two well regions, for example. Moreover, the residual metal can be prevented from reaching another PN junction portion in the semiconductor layer, for example, a PN junction portion of a well region and a source-drain region, a silicide can be prevented from being formed in the PN junction portion and the junction leakage current can be prevented from being generated.
According to the twenty-second aspect of the present invention, it is possible to obtain an SOI semiconductor device which is affected by metal pollution with difficulty.
According to the twenty-third aspect of the present invention, the unreacted metal layer is removed and the surface of the isolation film is removed by a predetermined thickness after the heat treatment for siliciding in the formation of the silicide layer. Therefore, the residual metal can be prevented from remaining on the isolation film and the residual metal can be prevented from being diffused into the isolation film by the heat treatment in the process and being silicided in an undesirable portion. For example, a silicide can be prevented from being formed in a PN junction portion and a junction leakage current can be prevented from being generated. Moreover, it is possible to prevent the silicide from being formed in the vicinity of an interface between the gate insulating film and the silicon layer. Thus, reliability of the gate insulating film can be maintained.
According to the twenty-fourth aspect of the present invention, the wet etching and the dry etching are carried out through two-time etching and hydrofluoric acid is used as the etching agent at the step (c-2). Consequently, the isolation film is removed together. Thus, it is possible to reliably prevent the residual metal from remaining on the isolation oxide film.
According to the twenty-fifth aspect of the present invention, portions other than the top of the isolation film are protected by a mask. Therefore, only the top of the isolation film is removed and other portions can be protected for the second removal of the unreacted metal layer.
According to the twenty-sixth aspect of the present invention, the isolation film having the polysilicon film therein can be obtained relatively easily.
According to the twenty-seventh aspect of the present invention, it is possible to obtain such a structure that the polysilicon film is insulated therein.
According to the twenty-eighth aspect of the present invention, it is possible to relatively easily obtain such a structure that the polysilicon film is insulated therein.
According to the twenty-ninth aspect of the present invention, it is possible to relatively easily obtain the isolation film having the nitride film therein.
According to the thirtieth aspect of the present invention, it is possible to relatively easily obtain the isolation film having such a structure that the complete trench and the partial trench are provided continuously, and having the internal polysilicon film provided to fill in the complete trench and to be extended over the bottom face of the partial trench.
According to the thirty-first aspect of the present invention, it is possible to obtain such a structure that the local crystal defect region is provided along the PN junction in the vicinity of the PN junction portion on at least one of sides in the two semiconductor regions.
According to the thirty-second aspect of the present invention, the crystal defect region is formed by introducing the impurity of the same conductivity type as the conductivity type of the semiconductor region in a relatively high concentration. Therefore, it is possible to reduce the influence on the well region through the impurity introduction.
According to the thirty-third aspect of the present invention, the crystal defect region is formed by introducing the impurity of a different conductivity type from the conductivity type of the semiconductor region in a relatively high concentration. Therefore, it is possible to increase the degree of freedom in selection of the method of forming the crystal defect region.
According to the thirty-fourth aspect of the present invention, it is possible to obtain such a structure that the upper nitride film is provided on the isolation film at the same step as the step of forming the side wall spacer of the MOS transistor.
According to the thirty-fifth aspect of the present invention, the first upper nitride film can be formed at the step of forming the first side wall spacer, the source drain region can be then formed and the second upper nitride film is thereafter formed at the step of forming the second side wall spacer. Consequently, the total formation width of the side wall spacer can be increased and drawbacks can be prevented from being caused by the abnormal growth of the silicide film. In addition, the extension region to be generally formed under the first side wall spacer can be shortened, a parasitic resistance can be reduced and the characteristic of the MOS transistor is not deteriorated.
According to the thirty-sixth aspect of the present invention, it is possible to obtain the isolation film having a plurality of silicon islands therein.
According to the thirty-seventh aspect of the present invention, the polysilicon film is connected to have the predetermined electric potential. Therefore, the isolation oxide film can be caused to function as a field shield isolating structure.
In order to solve the above-mentioned problems, it is an object of the present invention to provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.